249 lines
7.1 KiB
C
249 lines
7.1 KiB
C
/*******************************************************************************
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This module contains WINC3400 bus APIs implementation.
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File Name:
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nmbus.c
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Summary:
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This module contains WINC3400 bus APIs implementation.
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Description:
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This module contains WINC3400 bus APIs implementation.
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*******************************************************************************/
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//DOM-IGNORE-BEGIN
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/*******************************************************************************
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* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software
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* and any derivatives exclusively with Microchip products. It is your
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* responsibility to comply with third party license terms applicable to your
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* use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
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* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*******************************************************************************/
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#include "nmbus.h"
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#include "nmspi.h"
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#define MAX_TRX_CFG_SZ 8
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#define NM_BUS_MAX_TRX_SZ 256
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/**
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* @struct tstrNmBusCapabilities
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* @brief Structure holding bus capabilities information
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* @sa NM_BUS_TYPE_I2C, NM_BUS_TYPE_SPI
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*/
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typedef struct
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{
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uint16_t u16MaxTrxSz; /*!< Maximum transfer size. Must be >= 16 bytes*/
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} tstrNmBusCapabilities;
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tstrNmBusCapabilities egstrNmBusCapabilities =
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{
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NM_BUS_MAX_TRX_SZ
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};
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/*
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* @fn nm_bus_init
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* @brief Initialize the bus wrapper
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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static int8_t nm_bus_init(void *pvinit)
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{
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nm_reset();
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nm_sleep(1);
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return M2M_SUCCESS;
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}
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/*
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* @fn nm_bus_deinit
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* @brief De-initialize the bus wrapper
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*/
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static int8_t nm_bus_deinit(void)
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{
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return M2M_SUCCESS;
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}
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/**
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* @fn nm_bus_iface_init
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* @brief Initialize bus interface
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_bus_iface_init(void *pvInitVal)
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{
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int8_t ret = M2M_SUCCESS;
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ret = nm_bus_init(pvInitVal);
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return ret;
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}
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/**
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* @fn nm_bus_iface_deinit
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* @brief Deinitialize bus interface
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_bus_iface_deinit(void)
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{
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int8_t ret = M2M_SUCCESS;
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ret = nm_bus_deinit();
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return ret;
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}
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/**
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* @fn nm_bus_reset
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* @brief reset bus interface
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @version 1.0
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*/
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int8_t nm_bus_reset(void)
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{
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return nm_spi_reset();
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}
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/**
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* @fn nm_bus_iface_reconfigure
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* @brief reconfigure bus interface
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_bus_iface_reconfigure(void *ptr)
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{
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int8_t ret = M2M_SUCCESS;
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return ret;
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}
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/*
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* @fn nm_read_reg
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* @brief Read register
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* @param[in] u32Addr
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* Register address
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* @return Register value
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*/
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uint32_t nm_read_reg(uint32_t u32Addr)
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{
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return nm_spi_read_reg(u32Addr);
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}
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/*
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* @fn nm_read_reg_with_ret
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* @brief Read register with error code return
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* @param[in] u32Addr
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* Register address
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* @param[out] pu32RetVal
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* Pointer to u32 variable used to return the read value
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_read_reg_with_ret(uint32_t u32Addr, uint32_t* pu32RetVal)
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{
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return nm_spi_read_reg_with_ret(u32Addr, pu32RetVal);
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}
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/*
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* @fn nm_write_reg
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* @brief write register
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* @param[in] u32Addr
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* Register address
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* @param[in] u32Val
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* Value to be written to the register
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_write_reg(uint32_t u32Addr, uint32_t u32Val)
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{
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return nm_spi_write_reg(u32Addr, u32Val);
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}
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static inline int8_t p_nm_read_block(uint32_t u32Addr, uint8_t *puBuf, uint16_t u16Sz)
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{
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return nm_spi_read_block(u32Addr, puBuf, u16Sz);
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}
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/*
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* @fn nm_read_block
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* @brief Read block of data
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* @param[in] u32Addr
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* Start address
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* @param[out] puBuf
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* Pointer to a buffer used to return the read data
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* @param[in] u32Sz
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* Number of bytes to read. The buffer size must be >= u32Sz
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_read_block(uint32_t u32Addr, uint8_t *puBuf, uint32_t u32Sz)
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{
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uint16_t u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ;
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uint32_t off = 0;
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int8_t s8Ret = M2M_SUCCESS;
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for(;;)
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{
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if(u32Sz <= u16MaxTrxSz)
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{
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s8Ret += p_nm_read_block(u32Addr, &puBuf[off], (uint16_t)u32Sz);
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break;
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}
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else
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{
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s8Ret += p_nm_read_block(u32Addr, &puBuf[off], u16MaxTrxSz);
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if(M2M_SUCCESS != s8Ret) break;
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u32Sz -= u16MaxTrxSz;
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off += u16MaxTrxSz;
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u32Addr += u16MaxTrxSz;
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}
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}
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return s8Ret;
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}
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static inline int8_t p_nm_write_block(uint32_t u32Addr, uint8_t *puBuf, uint16_t u16Sz)
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{
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return nm_spi_write_block(u32Addr, puBuf, u16Sz);
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}
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/**
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* @fn nm_write_block
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* @brief Write block of data
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* @param[in] u32Addr
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* Start address
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* @param[in] puBuf
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* Pointer to the buffer holding the data to be written
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* @param[in] u32Sz
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* Number of bytes to write. The buffer size must be >= u32Sz
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* @return @ref M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_write_block(uint32_t u32Addr, uint8_t *puBuf, uint32_t u32Sz)
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{
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uint16_t u16MaxTrxSz = egstrNmBusCapabilities.u16MaxTrxSz - MAX_TRX_CFG_SZ;
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uint32_t off = 0;
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int8_t s8Ret = M2M_SUCCESS;
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for(;;)
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{
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if(u32Sz <= u16MaxTrxSz)
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{
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s8Ret += p_nm_write_block(u32Addr, &puBuf[off], (uint16_t)u32Sz);
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break;
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}
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else
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{
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s8Ret += p_nm_write_block(u32Addr, &puBuf[off], u16MaxTrxSz);
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if(M2M_SUCCESS != s8Ret) break;
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u32Sz -= u16MaxTrxSz;
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off += u16MaxTrxSz;
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u32Addr += u16MaxTrxSz;
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}
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}
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return s8Ret;
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}
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//DOM-IGNORE-END
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