149 lines
4.9 KiB
C
149 lines
4.9 KiB
C
/*******************************************************************************
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This module contains WINC3400 ASIC specific internal APIs.
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File Name:
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nmasic.h
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Summary:
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This module contains WINC3400 ASIC specific internal APIs.
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Description:
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This module contains WINC3400 ASIC specific internal APIs.
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*******************************************************************************/
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//DOM-IGNORE-BEGIN
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/*******************************************************************************
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* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software
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* and any derivatives exclusively with Microchip products. It is your
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* responsibility to comply with third party license terms applicable to your
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* use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
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* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*******************************************************************************/
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// DOM-IGNORE-END
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#ifndef _NMASIC_H_
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#define _NMASIC_H_
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#include "nm_common.h"
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#define NMI_PERIPH_REG_BASE 0x1000
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#define NMI_CHIPID (NMI_PERIPH_REG_BASE)
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#define rNMI_GP_REG_0 (0x149c)
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#define rNMI_GP_REG_1 (0x14A0)
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#define rNMI_GLB_RESET (0x1400)
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#define rNMI_BOOT_RESET_MUX (0x1118)
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#define NMI_STATE_REG (0x108c)
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#define BOOTROM_REG (0xc000c)
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#define NMI_REV_REG (0x207ac) /*Also, Used to load ATE firmware from SPI Flash and to ensure that it is running too*/
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#define M2M_WAIT_FOR_HOST_REG (0x207bc)
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#define M2M_FINISH_INIT_STATE 0x02532636UL
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#define M2M_FINISH_BOOT_ROM 0x10add09eUL
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#define M2M_START_FIRMWARE 0xef522f61UL
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#define M2M_START_PS_FIRMWARE 0x94992610UL
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#define M2M_ATE_FW_START_VALUE (0x3C1CD57D) /*Also, Change this value in boot_firmware if it will be changed here*/
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#define M2M_ATE_FW_IS_UP_VALUE (0xD75DC1C3) /*Also, Change this value in ATE (Burst) firmware if it will be changed here*/
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#define REV_2B0 (0x2B0)
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#define REV_B0 (0x2B0)
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#define REV_3A0 (0x3A0)
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#define CHIP_ID_3000D (0x3000D0)
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#define GET_CHIPID() nmi_get_chipid()
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#define ISNMC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0)
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#define ISNMC1500(id) (((id & 0xfffff000) == 0x150000) ? 1 : 0)
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#define ISNMC3400(id) (((id & 0xfff0f000) == 0x300000) ? 1 : 0)
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#define REV(id) ( ((id) & 0x00000fff ) )
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#define EFUSED_MAC(value) (value & 0xffff0000)
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#define rHAVE_SDIO_IRQ_GPIO_BIT (NBIT0)
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#define rHAVE_USE_PMU_BIT (NBIT1)
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#define rHAVE_SLEEP_CLK_SRC_RTC_BIT (NBIT2)
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#define rHAVE_SLEEP_CLK_SRC_XO_BIT (NBIT3)
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#define rHAVE_EXT_PA_INV_TX_RX (NBIT4)
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#define rHAVE_LEGACY_RF_SETTINGS (NBIT5)
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#define rHAVE_LOGS_DISABLED_BIT (NBIT6)
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#define rHAVE_ETHERNET_MODE_BIT (NBIT7)
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typedef struct {
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uint32_t u32Mac_efuse_mib;
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uint32_t u32Firmware_Ota_rev;
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} tstrGpRegs;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @fn nm_clkless_wake
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* @brief Wakeup the chip using clockless registers
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* @return ZERO in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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int8_t nm_clkless_wake(void);
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int8_t chip_wake(void);
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int8_t chip_sleep(void);
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void chip_idle(void);
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void enable_rf_blocks(void);
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int8_t enable_interrupts(void);
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int8_t cpu_start(void);
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uint32_t nmi_get_chipid(void);
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uint32_t nmi_get_rfrevid(void);
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void restore_pmu_settings_after_global_reset(void);
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void nmi_update_pll(void);
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void nmi_set_sys_clk_src_to_xo(void);
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int8_t chip_reset(void);
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int8_t wait_for_bootrom(uint8_t);
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int8_t wait_for_firmware_start(uint8_t);
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int8_t chip_deinit(void);
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int8_t chip_reset_and_cpu_halt(void);
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int8_t set_gpio_dir(uint8_t gpio, uint8_t dir);
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int8_t set_gpio_val(uint8_t gpio, uint8_t val);
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int8_t get_gpio_val(uint8_t gpio, uint8_t* val);
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int8_t pullup_ctrl(uint32_t pinmask, uint8_t enable);
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int8_t nmi_get_otp_mac_address(uint8_t *pu8MacAddr, uint8_t * pu8IsValid);
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int8_t nmi_get_mac_address(uint8_t *pu8MacAddr);
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int8_t chip_apply_conf(uint32_t u32conf);
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#ifdef __cplusplus
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}
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#endif
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#endif /*_NMASIC_H_*/
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