707 lines
18 KiB
C
707 lines
18 KiB
C
/*******************************************************************************
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File Name:
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nmasic.c
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Summary:
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This module contains WINC3400 ASIC specific internal APIs.
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Description:
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This module contains WINC3400 ASIC specific internal APIs.
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*******************************************************************************/
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//DOM-IGNORE-BEGIN
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/*******************************************************************************
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* Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software
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* and any derivatives exclusively with Microchip products. It is your
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* responsibility to comply with third party license terms applicable to your
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* use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER
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* EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
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* WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
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* PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
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* INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
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* WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
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* BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
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* FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN
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* ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*******************************************************************************/
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#include "nm_common.h"
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#include "nmbus.h"
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#include "nm_bsp.h"
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#include "nmasic.h"
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#include "m2m_types.h"
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#define NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400)
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#define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE + 0xa00)
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#define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)
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#define NMI_INTR_ENABLE (NMI_INTR_REG_BASE)
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#define GET_UINT32(X,Y) (X[0+Y] + ((uint32_t)X[1+Y]<<8) + ((uint32_t)X[2+Y]<<16) +((uint32_t)X[3+Y]<<24))
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#define CORT_HOST_COMM (0x14)
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#define HOST_CORT_COMM (0x0e)
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#define WAKE_CLK_REG (0x1)
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#define CLOCKS_EN_REG (0x13)
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#define TIMEOUT (2000)
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#define WAKEUP_TRIALS (4)
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int8_t chip_apply_conf(uint32_t u32Conf)
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{
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int8_t ret = M2M_SUCCESS;
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uint32_t val32 = u32Conf;
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#ifdef __ENABLE_PMU__
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val32 |= rHAVE_USE_PMU_BIT;
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#endif
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#ifdef __ENABLE_SLEEP_CLK_SRC_RTC__
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val32 |= rHAVE_SLEEP_CLK_SRC_RTC_BIT;
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#elif defined __ENABLE_SLEEP_CLK_SRC_XO__
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val32 |= rHAVE_SLEEP_CLK_SRC_XO_BIT;
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#endif
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#ifdef __ENABLE_EXT_PA_INV_TX_RX__
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val32 |= rHAVE_EXT_PA_INV_TX_RX;
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#endif
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#ifdef __ENABLE_LEGACY_RF_SETTINGS__
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val32 |= rHAVE_LEGACY_RF_SETTINGS;
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#endif
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#ifdef __DISABLE_FIRMWARE_LOGS__
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val32 |= rHAVE_LOGS_DISABLED_BIT;
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#endif
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do {
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nm_write_reg(rNMI_GP_REG_1, val32);
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if(val32 != 0) {
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uint32_t reg = 0;
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ret = nm_read_reg_with_ret(rNMI_GP_REG_1, ®);
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if(ret == M2M_SUCCESS) {
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if(reg == val32)
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break;
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}
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} else {
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break;
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}
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} while(1);
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return M2M_SUCCESS;
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}
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void chip_idle(void)
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{
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uint32_t reg =0;
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nm_read_reg_with_ret(WAKE_CLK_REG, ®);
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if(reg&NBIT1)
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{
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reg &=~NBIT1;
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nm_write_reg(WAKE_CLK_REG, reg);
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}
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}
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void enable_rf_blocks(void)
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{
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nm_write_reg(0x6, 0xdb);
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nm_write_reg(0x7, 0x6);
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nm_sleep(10);
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nm_write_reg(0x1480, 0);
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nm_write_reg(0x1484, 0);
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nm_sleep(10);
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nm_write_reg(0x6, 0x0);
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nm_write_reg(0x7, 0x0);
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}
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int8_t enable_interrupts(void)
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{
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uint32_t reg = 0;
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int8_t ret = M2M_SUCCESS;
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/**
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interrupt pin mux select
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**/
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ret = nm_read_reg_with_ret(NMI_PIN_MUX_0, ®);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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reg |= ((uint32_t) 1 << 8);
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ret = nm_write_reg(NMI_PIN_MUX_0, reg);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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/**
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interrupt enable
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**/
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ret = nm_read_reg_with_ret(NMI_INTR_ENABLE, ®);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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reg |= ((uint32_t) 1 << 16);
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ret = nm_write_reg(NMI_INTR_ENABLE, reg);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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return M2M_SUCCESS;
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}
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int8_t cpu_start(void) {
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uint32_t reg = 0;
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int8_t ret;
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/**
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reset regs
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*/
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ret = nm_write_reg(BOOTROM_REG, 0);
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ret += nm_write_reg(NMI_STATE_REG, 0);
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ret += nm_write_reg(NMI_REV_REG, 0);
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/**
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Go...
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**/
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ret += nm_read_reg_with_ret(0x1118, ®);
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if (M2M_SUCCESS != ret) {
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ret = M2M_ERR_BUS_FAIL;
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M2M_ERR("[nmi start]: fail read reg 0x1118 ...\r\n");
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}
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reg |= NBIT0;
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ret += nm_write_reg(0x1118, reg);
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ret = nm_write_reg(0x150014, 0x1); //DTODO WHY IS THIS HERE??
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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if ((reg & (1ul << 10)) == (1ul << 10)) {
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reg &= ~(1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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}
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reg |= (1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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nm_sleep(1); /* Removing this can cause a bus error. */
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return ret;
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}
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uint32_t nmi_get_chipid(void)
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{
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static uint32_t chipid = 0;
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if (chipid == 0) {
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uint32_t rfrevid;
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if ((nm_read_reg_with_ret(0x1000, &chipid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if ((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if (chipid == 0x1002a0) {
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if (rfrevid == 0x1) { /* 1002A0 */
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} else /* if (rfrevid == 0x2) */ { /* 1002A1 */
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chipid = 0x1002a1;
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}
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} else if (chipid == 0x1002b0) {
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if (rfrevid == 3) { /* 1002B0 */
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} else if (rfrevid == 4) { /* 1002B1 */
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chipid = 0x1002b1;
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} else /* if(rfrevid == 5) */ { /* 1002B2 */
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chipid = 0x1002b2;
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}
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} else if(chipid == 0x1000f0) {
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/* For 3400, the WiFi chip ID register reads 0x1000f0.
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* Therefore using BT chip ID register here which should read 0x3000D0
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*/
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#define rBT_CHIP_ID_REG (0x3b0000)
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if((nm_read_reg_with_ret(rBT_CHIP_ID_REG, &chipid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if(chipid == 0x3000d0) {
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if(rfrevid == 6) {
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chipid = 0x3000d1;
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}
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else if(rfrevid == 2) {
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chipid = 0x3000d2;
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}
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}
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}
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//#define PROBE_FLASH
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#ifdef PROBE_FLASH
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if(chipid) {
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UWORD32 flashid;
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flashid = probe_spi_flash();
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if((chipid & 0xf00000) == 0x300000) {
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if(flashid == 0x1440ef) {
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chipid &= ~(0x0f0000);
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chipid |= 0x040000;
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}
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} else {
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if(flashid == 0x1230ef) {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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if(flashid == 0xc21320c2) {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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}
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}
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#else
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/*M2M is by default have SPI flash*/
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if((chipid & 0xf00000) == 0x300000) {
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chipid &= ~(0x0f0000);
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chipid |= 0x040000;
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} else {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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#endif /* PROBE_FLASH */
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}
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return chipid;
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}
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uint32_t nmi_get_rfrevid(void)
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{
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uint32_t rfrevid;
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if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
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rfrevid = 0;
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}
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return rfrevid;
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}
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void restore_pmu_settings_after_global_reset(void)
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{
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/*
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* Must restore PMU register value after
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* global reset if PMU toggle is done at
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* least once since the last hard reset.
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*/
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if(REV(nmi_get_chipid()) >= REV_2B0) {
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nm_write_reg(0x1e48, 0xb78469ce);
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}
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}
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void nmi_update_pll(void)
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{
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uint32_t pll;
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pll = nm_read_reg(0x1428);
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pll &= ~0x1ul;
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nm_write_reg(0x1428, pll);
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pll |= 0x1ul;
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nm_write_reg(0x1428, pll);
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}
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void nmi_set_sys_clk_src_to_xo(void)
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{
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uint32_t val32;
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/* Switch system clock source to XO. This will take effect after nmi_update_pll(). */
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val32 = nm_read_reg(0x141c);
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val32 |= (1 << 2);
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nm_write_reg(0x141c, val32);
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/* Do PLL update */
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nmi_update_pll();
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}
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int8_t chip_sleep(void)
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{
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uint32_t reg;
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int8_t ret = M2M_SUCCESS;
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while(1)
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{
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ret = nm_read_reg_with_ret(CORT_HOST_COMM, ®);
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if(ret != M2M_SUCCESS) goto ERR1;
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if((reg & NBIT0) == 0) break;
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}
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/* Clear bit 1 */
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ret = nm_read_reg_with_ret(WAKE_CLK_REG, ®);
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if(ret != M2M_SUCCESS)goto ERR1;
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if(reg & NBIT1)
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{
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reg &=~NBIT1;
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ret = nm_write_reg(WAKE_CLK_REG, reg);
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if(ret != M2M_SUCCESS)goto ERR1;
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}
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ret = nm_read_reg_with_ret(HOST_CORT_COMM, ®);
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if(ret != M2M_SUCCESS)goto ERR1;
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if(reg & NBIT0)
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{
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reg &= ~NBIT0;
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ret = nm_write_reg(HOST_CORT_COMM, reg);
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if(ret != M2M_SUCCESS)goto ERR1;
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}
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ERR1:
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return ret;
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}
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int8_t chip_wake(void)
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{
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int8_t ret = M2M_SUCCESS;
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uint32_t reg = 0, clk_status_reg = 0, trials = 0;
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nm_read_reg_with_ret(CLOCKS_EN_REG, &clk_status_reg);
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ret = nm_read_reg_with_ret(HOST_CORT_COMM, ®);
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if(ret != M2M_SUCCESS)goto _WAKE_EXIT;
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if(!(reg & NBIT0))
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{
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/*USE bit 0 to indicate host wakeup*/
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ret = nm_write_reg(HOST_CORT_COMM, reg|NBIT0);
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if(ret != M2M_SUCCESS)goto _WAKE_EXIT;
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}
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ret = nm_read_reg_with_ret(WAKE_CLK_REG, ®);
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if(ret != M2M_SUCCESS) goto _WAKE_EXIT;
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/* Set bit 1 */
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if(!(reg & NBIT1))
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{
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ret = nm_write_reg(WAKE_CLK_REG, reg | NBIT1);
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if(ret != M2M_SUCCESS) goto _WAKE_EXIT;
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}
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do
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{
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ret = nm_read_reg_with_ret(CLOCKS_EN_REG, &clk_status_reg);
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if(ret != M2M_SUCCESS) {
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M2M_ERR("Bus error (5).%d %" PRIx32 "\n", ret, clk_status_reg);
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goto _WAKE_EXIT;
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}
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if (clk_status_reg & NBIT2) {
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break;
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}
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nm_sleep(2);
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trials++;
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if (trials > WAKEUP_TRIALS)
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{
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M2M_ERR("Failed to wakeup the chip\n");
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ret = M2M_ERR_TIME_OUT;
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goto _WAKE_EXIT;
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}
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} while(1);
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/* Workaround sometimes spi fail to read clock regs after reading/writing clockless registers */
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//nm_bus_reset();
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_WAKE_EXIT:
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return ret;
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}
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int8_t chip_reset_and_cpu_halt(void)
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{
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int8_t ret = M2M_SUCCESS;
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uint32_t reg = 0;
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ret = chip_wake();
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if (ret != M2M_SUCCESS) {
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return ret;
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}
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chip_reset();
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ret = nm_read_reg_with_ret(0x1118, ®);
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if (M2M_SUCCESS != ret) {
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ret = M2M_ERR_BUS_FAIL;
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M2M_ERR("[nmi start]: fail read reg 0x1118 ...\r\n");
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}
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reg |= (1 << 0);
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ret = nm_write_reg(0x1118, reg);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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if ((reg & (1ul << 10)) == (1ul << 10)) {
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reg &= ~(1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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}
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nm_write_reg(BOOTROM_REG, 0);
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nm_write_reg(NMI_STATE_REG, 0);
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nm_write_reg(NMI_REV_REG, 0);
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nm_write_reg(NMI_PIN_MUX_0, 0x11111000);
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return ret;
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}
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int8_t chip_reset(void)
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{
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int8_t ret = M2M_SUCCESS;
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ret += nm_write_reg(NMI_GLB_RESET_0, 0);
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nm_sleep(50);
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return ret;
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}
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int8_t wait_for_bootrom(uint8_t arg)
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{
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int8_t ret = M2M_SUCCESS;
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uint32_t reg = 0, cnt = 0;
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uint32_t u32GpReg1 = 0;
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reg = 0;
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while(1) {
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reg = nm_read_reg(0x1014); /* wait for efuse loading done */
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if (reg & 0x80000000) {
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break;
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}
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nm_sleep(1); /* Removing this can cause a bus error. */
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}
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reg = nm_read_reg(M2M_WAIT_FOR_HOST_REG);
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reg &= 0x1;
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/* check if waiting for the host will be skipped or not */
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if(reg == 0)
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{
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while(reg != M2M_FINISH_BOOT_ROM)
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{
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nm_sleep(1);
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reg = nm_read_reg(BOOTROM_REG);
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if (++cnt > TIMEOUT)
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{
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M2M_DBG("failed to load firmware from flash.\r\n");
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ret = M2M_ERR_INIT;
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goto ERR2;
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}
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}
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}
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if (M2M_WIFI_MODE_CONFIG == arg) {
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nm_write_reg(NMI_REV_REG, M2M_ATE_FW_START_VALUE);
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} else if (M2M_WIFI_MODE_ETHERNET == arg) {
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u32GpReg1 = rHAVE_ETHERNET_MODE_BIT;
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} else {
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/*bypass this step*/
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}
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if (REV(nmi_get_chipid()) == REV_3A0)
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{
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chip_apply_conf(u32GpReg1 | rHAVE_USE_PMU_BIT);
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}
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else
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{
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chip_apply_conf(u32GpReg1);
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}
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nm_write_reg(BOOTROM_REG, M2M_START_FIRMWARE);
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#ifdef __ROM_TEST__
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rom_test();
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#endif /* __ROM_TEST__ */
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ERR2:
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return ret;
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}
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int8_t wait_for_firmware_start(uint8_t arg)
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{
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int8_t ret = M2M_SUCCESS;
|
|
uint32_t reg = 0, cnt = 0;
|
|
volatile uint32_t regAddress = NMI_STATE_REG;
|
|
volatile uint32_t checkValue = M2M_FINISH_INIT_STATE;
|
|
|
|
if(M2M_WIFI_MODE_CONFIG == arg) {
|
|
regAddress = NMI_REV_REG;
|
|
checkValue = M2M_ATE_FW_START_VALUE;//M2M_ATE_FW_IS_UP_VALUE;
|
|
} else {
|
|
/*bypass this step*/
|
|
}
|
|
|
|
while (checkValue != reg)
|
|
{
|
|
nm_sleep(2); /* Removing this can cause a bus error. */
|
|
M2M_DBG("%x %x %x\r\n", (unsigned int)nm_read_reg(0x108c), (unsigned int)nm_read_reg(0x108c), (unsigned int)nm_read_reg(0x14A0));
|
|
if (nm_read_reg_with_ret(regAddress, ®) != M2M_SUCCESS)
|
|
{
|
|
// ensure reg != checkValue
|
|
reg = !checkValue;
|
|
}
|
|
if (++cnt > TIMEOUT)
|
|
{
|
|
M2M_DBG("Time out for wait firmware Run\r\n");
|
|
ret = M2M_ERR_INIT;
|
|
goto ERR;
|
|
}
|
|
}
|
|
if (M2M_FINISH_INIT_STATE == checkValue)
|
|
{
|
|
nm_write_reg(NMI_STATE_REG, 0);
|
|
}
|
|
ERR:
|
|
return ret;
|
|
}
|
|
|
|
int8_t chip_deinit(void)
|
|
{
|
|
uint32_t reg = 0;
|
|
int8_t ret;
|
|
uint8_t timeout = 10;
|
|
|
|
/**
|
|
stop the firmware, need a re-download
|
|
**/
|
|
ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("failed to de-initialize\r\n");
|
|
}
|
|
reg &= ~(1 << 10);
|
|
ret = nm_write_reg(NMI_GLB_RESET_0, reg);
|
|
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("Error while writing reg\r\n");
|
|
return ret;
|
|
}
|
|
|
|
do {
|
|
ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("Error while reading reg\r\n");
|
|
return ret;
|
|
}
|
|
/*Workaround to ensure that the chip is actually reset*/
|
|
if ((reg & (1 << 10))) {
|
|
M2M_DBG("Bit 10 not reset retry %d\r\n", timeout);
|
|
reg &= ~(1 << 10);
|
|
ret = nm_write_reg(NMI_GLB_RESET_0, reg);
|
|
timeout--;
|
|
} else {
|
|
break;
|
|
}
|
|
} while (timeout);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int8_t set_gpio_dir(uint8_t gpio, uint8_t dir)
|
|
{
|
|
uint32_t val32;
|
|
int8_t ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20108, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
if(dir) {
|
|
val32 |= (1ul << gpio);
|
|
} else {
|
|
val32 &= ~(1ul << gpio);
|
|
}
|
|
|
|
ret = nm_write_reg(0x20108, val32);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
int8_t set_gpio_val(uint8_t gpio, uint8_t val)
|
|
{
|
|
uint32_t val32;
|
|
int8_t ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20100, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
if(val) {
|
|
val32 |= (1ul << gpio);
|
|
} else {
|
|
val32 &= ~(1ul << gpio);
|
|
}
|
|
|
|
ret = nm_write_reg(0x20100, val32);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
|
|
int8_t get_gpio_val(uint8_t gpio, uint8_t* val)
|
|
{
|
|
uint32_t val32;
|
|
int8_t ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20104, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
*val = (uint8_t)((val32 >> gpio) & 0x01);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
|
|
int8_t pullup_ctrl(uint32_t pinmask, uint8_t enable)
|
|
{
|
|
int8_t s8Ret;
|
|
uint32_t val32;
|
|
s8Ret = nm_read_reg_with_ret(0x142c, &val32);
|
|
if (s8Ret != M2M_SUCCESS) {
|
|
M2M_ERR("[pullup_ctrl]: failed to read\r\n");
|
|
goto _EXIT;
|
|
}
|
|
if (enable) {
|
|
val32 &= ~pinmask;
|
|
} else {
|
|
val32 |= pinmask;
|
|
}
|
|
s8Ret = nm_write_reg(0x142c, val32);
|
|
if (s8Ret != M2M_SUCCESS) {
|
|
M2M_ERR("[pullup_ctrl]: failed to write\r\n");
|
|
goto _EXIT;
|
|
}
|
|
_EXIT:
|
|
return s8Ret;
|
|
}
|
|
|
|
int8_t nmi_get_otp_mac_address(uint8_t *pu8MacAddr, uint8_t *pu8IsValid)
|
|
{
|
|
int8_t ret;
|
|
uint32_t u32RegValue;
|
|
uint8_t mac[6];
|
|
tstrGpRegs strgp = {0};
|
|
|
|
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
|
|
if (ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
|
|
ret = nm_read_block(u32RegValue|0x30000,(uint8_t*)&strgp,sizeof(tstrGpRegs));
|
|
if (ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
u32RegValue = strgp.u32Mac_efuse_mib;
|
|
|
|
if (!EFUSED_MAC(u32RegValue)) {
|
|
M2M_DBG("Default MAC\r\n");
|
|
memset(pu8MacAddr, 0, 6);
|
|
goto _EXIT_ERR;
|
|
}
|
|
|
|
M2M_DBG("OTP MAC\r\n");
|
|
u32RegValue >>=16;
|
|
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
|
|
memcpy(pu8MacAddr, mac, 6);
|
|
if (pu8IsValid) *pu8IsValid = 1;
|
|
return ret;
|
|
|
|
_EXIT_ERR:
|
|
if (pu8IsValid) *pu8IsValid = 0;
|
|
return ret;
|
|
}
|
|
|
|
int8_t nmi_get_mac_address(uint8_t *pu8MacAddr)
|
|
{
|
|
int8_t ret;
|
|
uint32_t u32RegValue;
|
|
uint8_t mac[6];
|
|
tstrGpRegs strgp = {0};
|
|
|
|
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
|
|
if (ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
|
|
ret = nm_read_block(u32RegValue|0x30000, (uint8_t*)&strgp, sizeof(tstrGpRegs));
|
|
if (ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
u32RegValue = strgp.u32Mac_efuse_mib;
|
|
|
|
u32RegValue &=0x0000ffff;
|
|
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
|
|
memcpy(pu8MacAddr, mac, 6);
|
|
|
|
_EXIT_ERR:
|
|
return ret;
|
|
}
|
|
|
|
//DOM-IGNORE-END
|