742 lines
16 KiB
C
742 lines
16 KiB
C
/**
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*
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* \file
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*
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* \brief This module contains WINC3400 ASIC specific internal APIs.
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#include "common/include/nm_common.h"
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#include "driver/source/nmbus.h"
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#include "bsp/include/nm_bsp.h"
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#include "driver/source/nmasic.h"
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#define NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400)
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#define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE + 0xa00)
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#define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)
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#define NMI_INTR_ENABLE (NMI_INTR_REG_BASE)
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#define GET_UINT32(X,Y) (X[0+Y] + ((uint32)X[1+Y]<<8) + ((uint32)X[2+Y]<<16) +((uint32)X[3+Y]<<24))
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#define TIMEOUT (2000)
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#define M2M_DISABLE_PS 0xD0UL
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/* Assume initially we're dealing with D0 - we will try other addresses if this
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* fails - the addresses are as follows:
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* 0x13 - for D0
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* 0x0F - for B0
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* 0x0E - for A0
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*/
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static uint32 clk_status_reg_adr = 0x13;
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sint8 chip_apply_conf(uint32 u32Conf)
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{
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sint8 ret = M2M_SUCCESS;
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uint32 val32 = u32Conf;
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#ifdef __ENABLE_PMU__
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val32 |= rHAVE_USE_PMU_BIT;
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#endif
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#ifdef __ENABLE_SLEEP_CLK_SRC_RTC__
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val32 |= rHAVE_SLEEP_CLK_SRC_RTC_BIT;
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#elif defined __ENABLE_SLEEP_CLK_SRC_XO__
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val32 |= rHAVE_SLEEP_CLK_SRC_XO_BIT;
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#endif
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#ifdef __ENABLE_EXT_PA_INV_TX_RX__
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val32 |= rHAVE_EXT_PA_INV_TX_RX;
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#endif
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#ifdef __ENABLE_LEGACY_RF_SETTINGS__
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val32 |= rHAVE_LEGACY_RF_SETTINGS;
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#endif
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#ifdef __DISABLE_FIRMWARE_LOGS__
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val32 |= rHAVE_LOGS_DISABLED_BIT;
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#endif
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do {
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nm_write_reg(rNMI_GP_REG_1, val32);
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if(val32 != 0) {
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uint32 reg = 0;
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ret = nm_read_reg_with_ret(rNMI_GP_REG_1, ®);
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if(ret == M2M_SUCCESS) {
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if(reg == val32)
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break;
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}
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} else {
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break;
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}
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} while(1);
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return M2M_SUCCESS;
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}
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/**
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* @fn nm_clkless_wake
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* @brief Wakeup the chip using clockless registers
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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* @author Samer Sarhan
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* @date 06 June 2014
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* @version 1.0
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*/
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sint8 nm_clkless_wake(void)
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{
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sint8 ret = M2M_SUCCESS;
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uint32 reg, clk_status_reg,trials = 0;
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uint32 keeptrying = 200;
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/* wait 1ms, spi data read */
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nm_bsp_sleep(1);
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ret = nm_read_reg_with_ret(0x1, ®);
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if(ret != M2M_SUCCESS) {
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M2M_ERR("Bus error (1). Wake up failed\n");
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return ret;
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}
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/*
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* At this point, I am not sure whether it is B0 or A0
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* If B0, then clks_enabled bit exists in register 0xf
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* If A0, then clks_enabled bit exists in register 0xe
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*/
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do
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{
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/* Set bit 1 */
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nm_write_reg(0x1, reg | (1 << 1));
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// Search for the correct (clock status) register address
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do
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{
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if (keeptrying) --keeptrying;
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/* wait 1ms, spi data read */
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nm_bsp_sleep(1);
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ret = nm_read_reg_with_ret(clk_status_reg_adr, &clk_status_reg);
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if (ret != M2M_SUCCESS || (ret == M2M_SUCCESS && clk_status_reg == 0)) {
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switch (clk_status_reg_adr) {
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case 0x13: clk_status_reg_adr = 0x0F; break;
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case 0x0F: clk_status_reg_adr = 0x0E; break;
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default: clk_status_reg_adr = 0x00; break;
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}
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}
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else
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break; // we have found the correct register, break out of the search
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} while (clk_status_reg_adr && keeptrying);
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if (0 == clk_status_reg_adr) {
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M2M_ERR("Bus error (2). Wake up failed\n");
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return ret;
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}
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// in case of clocks off, wait 2ms, and check it again.
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// if still off, wait for another 2ms, for a total wait of 6ms.
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// If still off, redo the wake up sequence
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trials = 0;
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while( ((clk_status_reg & 0x4) == 0) && (((++trials) %3) == 0) && keeptrying)
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{
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--keeptrying;
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/* Wait for the chip to stabilize*/
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nm_bsp_sleep(2);
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// Make sure chip is awake. This is an extra step that can be removed
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// later to avoid the bus access overhead
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nm_read_reg_with_ret(clk_status_reg_adr, &clk_status_reg);
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if ((clk_status_reg & 0x4) == 0)
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{
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M2M_ERR("clocks still OFF. Wake up failed\n");
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}
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}
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// in case of failure, Reset the wakeup bit to introduce a new edge on the next loop
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if((clk_status_reg & 0x4) == 0)
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{
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// Reset bit 0
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nm_write_reg(0x1, reg | (1 << 1));
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}
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} while((clk_status_reg & 0x4) == 0 && keeptrying);
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if (!keeptrying)
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{
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M2M_ERR("Wake up failed - out of retries\n");
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ret = M2M_ERR_INIT;
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}
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return ret;
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}
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void chip_idle(void)
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{
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uint32 reg =0;
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nm_read_reg_with_ret(0x1, ®);
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if(reg&0x2)
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{
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reg &=~(1 << 1);
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nm_write_reg(0x1, reg);
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}
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}
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void enable_rf_blocks(void)
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{
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nm_write_reg(0x6, 0xdb);
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nm_write_reg(0x7, 0x6);
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nm_bsp_sleep(10);
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nm_write_reg(0x1480, 0);
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nm_write_reg(0x1484, 0);
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nm_bsp_sleep(10);
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nm_write_reg(0x6, 0x0);
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nm_write_reg(0x7, 0x0);
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}
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sint8 enable_interrupts(void)
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{
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uint32 reg;
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sint8 ret;
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/**
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interrupt pin mux select
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**/
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ret = nm_read_reg_with_ret(NMI_PIN_MUX_0, ®);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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reg |= ((uint32) 1 << 8);
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ret = nm_write_reg(NMI_PIN_MUX_0, reg);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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/**
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interrupt enable
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**/
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ret = nm_read_reg_with_ret(NMI_INTR_ENABLE, ®);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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reg |= ((uint32) 1 << 16);
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ret = nm_write_reg(NMI_INTR_ENABLE, reg);
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if (M2M_SUCCESS != ret) {
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return M2M_ERR_BUS_FAIL;
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}
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return M2M_SUCCESS;
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}
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sint8 cpu_start(void) {
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uint32 reg;
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sint8 ret;
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/**
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reset regs
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*/
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nm_write_reg(BOOTROM_REG,0);
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nm_write_reg(NMI_STATE_REG,0);
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nm_write_reg(NMI_REV_REG,0);
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/**
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Go...
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**/
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ret = nm_read_reg_with_ret(0x1118, ®);
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if (M2M_SUCCESS != ret) {
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ret = M2M_ERR_BUS_FAIL;
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M2M_ERR("[nmi start]: fail read reg 0x1118 ...\n");
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}
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reg |= (1 << 0);
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ret = nm_write_reg(0x1118, reg);
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ret = nm_write_reg(0x150014, 0x1);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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if ((reg & (1ul << 10)) == (1ul << 10)) {
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reg &= ~(1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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}
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reg |= (1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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nm_bsp_sleep(1); /* TODO: Why bus error if this delay is not here. */
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return ret;
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}
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uint32 nmi_get_chipid(void)
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{
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static uint32 chipid = 0;
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if (chipid == 0) {
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uint32 rfrevid;
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if((nm_read_reg_with_ret(0x1000, &chipid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if(chipid == 0x1002a0) {
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if (rfrevid == 0x1) { /* 1002A0 */
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} else /* if (rfrevid == 0x2) */ { /* 1002A1 */
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chipid = 0x1002a1;
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}
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} else if(chipid == 0x1002b0) {
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if(rfrevid == 3) { /* 1002B0 */
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} else if(rfrevid == 4) { /* 1002B1 */
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chipid = 0x1002b1;
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} else /* if(rfrevid == 5) */ { /* 1002B2 */
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chipid = 0x1002b2;
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}
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} else if(chipid == 0x1000f0) {
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/* For 3400, the WiFi chip ID register reads 0x1000f0.
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* Therefore using BT chip ID register here which should read 0x3000D0
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*/
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#define rBT_CHIP_ID_REG (0x3b0000)
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if((nm_read_reg_with_ret(rBT_CHIP_ID_REG, &chipid)) != M2M_SUCCESS) {
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chipid = 0;
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return 0;
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}
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if(chipid == 0x3000d0) {
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if(rfrevid == 6) {
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chipid = 0x3000d1;
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}
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else if(rfrevid == 2) {
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chipid = 0x3000d2;
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}
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}
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}
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//#define PROBE_FLASH
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#ifdef PROBE_FLASH
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if(chipid) {
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UWORD32 flashid;
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flashid = probe_spi_flash();
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if((chipid & 0xf00000) == 0x300000) {
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if(flashid == 0x1440ef) {
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chipid &= ~(0x0f0000);
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chipid |= 0x040000;
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}
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} else {
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if(flashid == 0x1230ef) {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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if(flashid == 0xc21320c2) {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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}
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}
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#else
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/*M2M is by default have SPI flash*/
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if((chipid & 0xf00000) == 0x300000) {
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chipid &= ~(0x0f0000);
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chipid |= 0x040000;
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} else {
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chipid &= ~(0x0f0000);
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chipid |= 0x050000;
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}
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#endif /* PROBE_FLASH */
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}
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return chipid;
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}
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uint32 nmi_get_rfrevid(void)
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{
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uint32 rfrevid;
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if((nm_read_reg_with_ret(0x13f4, &rfrevid)) != M2M_SUCCESS) {
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rfrevid = 0;
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return 0;
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}
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return rfrevid;
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}
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void restore_pmu_settings_after_global_reset(void)
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{
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/*
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* Must restore PMU register value after
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* global reset if PMU toggle is done at
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* least once since the last hard reset.
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*/
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if(REV(nmi_get_chipid()) >= REV_2B0) {
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nm_write_reg(0x1e48, 0xb78469ce);
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}
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}
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void nmi_update_pll(void)
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{
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uint32 pll;
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pll = nm_read_reg(0x1428);
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pll &= ~0x1ul;
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nm_write_reg(0x1428, pll);
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pll |= 0x1ul;
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nm_write_reg(0x1428, pll);
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}
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void nmi_set_sys_clk_src_to_xo(void)
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{
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uint32 val32;
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/* Switch system clock source to XO. This will take effect after nmi_update_pll(). */
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val32 = nm_read_reg(0x141c);
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val32 |= (1 << 2);
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nm_write_reg(0x141c, val32);
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/* Do PLL update */
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nmi_update_pll();
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}
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sint8 chip_wake(void)
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{
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sint8 ret = M2M_SUCCESS;
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ret = nm_clkless_wake();
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if(ret != M2M_SUCCESS) return ret;
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// enable_rf_blocks(); MERGEBUG: TEMPORARILY DISABLING
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return ret;
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}
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sint8 chip_reset_and_cpu_halt(void)
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{
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sint8 ret = M2M_SUCCESS;
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uint32 reg = 0;
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ret = chip_wake();
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if(ret != M2M_SUCCESS) {
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return ret;
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}
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chip_reset();
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ret = nm_read_reg_with_ret(0x1118, ®);
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if (M2M_SUCCESS != ret) {
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ret = M2M_ERR_BUS_FAIL;
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M2M_ERR("[nmi start]: fail read reg 0x1118 ...\n");
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}
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reg |= (1 << 0);
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ret = nm_write_reg(0x1118, reg);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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if ((reg & (1ul << 10)) == (1ul << 10)) {
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reg &= ~(1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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}
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#if 0
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reg |= (1ul << 10);
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ret += nm_write_reg(NMI_GLB_RESET_0, reg);
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ret += nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
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#endif
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nm_write_reg(BOOTROM_REG,0);
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nm_write_reg(NMI_STATE_REG,0);
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nm_write_reg(NMI_REV_REG,0);
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nm_write_reg(NMI_PIN_MUX_0, 0x11111000);
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return ret;
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}
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sint8 chip_reset(void)
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{
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sint8 ret = M2M_SUCCESS;
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#if 0
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// MERGEBUG: TODO: This causes serial trace from the chip to be garbled - investigate
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#ifndef CONF_WINC_USE_UART
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nmi_set_sys_clk_src_to_xo();
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#endif
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#endif
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ret += nm_write_reg(NMI_GLB_RESET_0, 0);
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nm_bsp_sleep(50);
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#ifndef CONF_WINC_USE_UART
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restore_pmu_settings_after_global_reset();
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#endif
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return ret;
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}
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sint8 wait_for_bootrom(uint8 arg)
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{
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sint8 ret = M2M_SUCCESS;
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uint32 reg = 0, cnt = 0;
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reg = 0;
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while(1) {
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reg = nm_read_reg(0x1014); /* wait for efuse loading done */
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if (reg & 0x80000000) {
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break;
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}
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nm_bsp_sleep(1); /* TODO: Why bus error if this delay is not here. */
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}
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reg = nm_read_reg(M2M_WAIT_FOR_HOST_REG);
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reg &= 0x1;
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/* check if waiting for the host will be skipped or not */
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if(reg == 0)
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{
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reg = 0;
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while(reg != M2M_FINISH_BOOT_ROM)
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{
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nm_bsp_sleep(1);
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reg = nm_read_reg(BOOTROM_REG);
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if(++cnt > TIMEOUT)
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{
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M2M_DBG("failed to load firmware from flash.\n");
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ret = M2M_ERR_INIT;
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goto ERR2;
|
|
}
|
|
}
|
|
}
|
|
|
|
if(2 == arg) {
|
|
nm_write_reg(NMI_REV_REG, M2M_ATE_FW_START_VALUE);
|
|
} else {
|
|
/*bypass this step*/
|
|
}
|
|
|
|
if(REV(nmi_get_chipid()) == REV_3A0)
|
|
{
|
|
chip_apply_conf(rHAVE_USE_PMU_BIT);
|
|
}
|
|
else
|
|
{
|
|
chip_apply_conf(0);
|
|
}
|
|
|
|
nm_write_reg(BOOTROM_REG,M2M_START_FIRMWARE);
|
|
|
|
#ifdef __ROM_TEST__
|
|
rom_test();
|
|
#endif /* __ROM_TEST__ */
|
|
|
|
ERR2:
|
|
return ret;
|
|
}
|
|
|
|
sint8 wait_for_firmware_start(uint8 arg)
|
|
{
|
|
sint8 ret = M2M_SUCCESS;
|
|
uint32 reg = 0, cnt = 0;
|
|
volatile uint32 regAddress = NMI_STATE_REG;
|
|
volatile uint32 checkValue = M2M_FINISH_INIT_STATE;
|
|
|
|
if(2 == arg) {
|
|
regAddress = NMI_REV_REG;
|
|
checkValue = M2M_ATE_FW_IS_UP_VALUE;
|
|
} else {
|
|
/*bypass this step*/
|
|
}
|
|
|
|
while (checkValue != reg)
|
|
{
|
|
nm_bsp_sleep(2); /* TODO: Why bus error if this delay is not here. */
|
|
M2M_DBG("%x %x %x\n",(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x108c),(unsigned int)nm_read_reg(0x14A0));
|
|
if (nm_read_reg_with_ret(regAddress, ®) != M2M_SUCCESS)
|
|
{
|
|
// ensure reg != checkValue
|
|
reg = !checkValue;
|
|
}
|
|
if(++cnt > TIMEOUT)
|
|
{
|
|
M2M_DBG("Time out for wait firmware Run\n");
|
|
ret = M2M_ERR_INIT;
|
|
goto ERR;
|
|
}
|
|
}
|
|
if(M2M_FINISH_INIT_STATE == checkValue)
|
|
{
|
|
nm_write_reg(NMI_STATE_REG, 0);
|
|
}
|
|
ERR:
|
|
return ret;
|
|
}
|
|
|
|
sint8 chip_deinit(void)
|
|
{
|
|
uint32 reg = 0;
|
|
sint8 ret;
|
|
uint8 timeout = 10;
|
|
|
|
/**
|
|
stop the firmware, need a re-download
|
|
**/
|
|
ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("failed to de-initialize\n");
|
|
}
|
|
reg &= ~(1 << 10);
|
|
ret = nm_write_reg(NMI_GLB_RESET_0, reg);
|
|
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("Error while writing reg\n");
|
|
return ret;
|
|
}
|
|
|
|
do {
|
|
ret = nm_read_reg_with_ret(NMI_GLB_RESET_0, ®);
|
|
if (ret != M2M_SUCCESS) {
|
|
M2M_ERR("Error while reading reg\n");
|
|
return ret;
|
|
}
|
|
/*Workaround to ensure that the chip is actually reset*/
|
|
if ((reg & (1 << 10))) {
|
|
M2M_DBG("Bit 10 not reset retry %d\n", timeout);
|
|
reg &= ~(1 << 10);
|
|
ret = nm_write_reg(NMI_GLB_RESET_0, reg);
|
|
timeout--;
|
|
} else {
|
|
break;
|
|
}
|
|
|
|
} while (timeout);
|
|
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONF_PERIPH
|
|
|
|
sint8 set_gpio_dir(uint8 gpio, uint8 dir)
|
|
{
|
|
uint32 val32;
|
|
sint8 ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20108, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
if(dir) {
|
|
val32 |= (1ul << gpio);
|
|
} else {
|
|
val32 &= ~(1ul << gpio);
|
|
}
|
|
|
|
ret = nm_write_reg(0x20108, val32);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
sint8 set_gpio_val(uint8 gpio, uint8 val)
|
|
{
|
|
uint32 val32;
|
|
sint8 ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20100, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
if(val) {
|
|
val32 |= (1ul << gpio);
|
|
} else {
|
|
val32 &= ~(1ul << gpio);
|
|
}
|
|
|
|
ret = nm_write_reg(0x20100, val32);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
|
|
sint8 get_gpio_val(uint8 gpio, uint8* val)
|
|
{
|
|
uint32 val32;
|
|
sint8 ret;
|
|
|
|
ret = nm_read_reg_with_ret(0x20104, &val32);
|
|
if(ret != M2M_SUCCESS) goto _EXIT;
|
|
|
|
*val = (uint8)((val32 >> gpio) & 0x01);
|
|
|
|
_EXIT:
|
|
return ret;
|
|
}
|
|
|
|
sint8 pullup_ctrl(uint32 pinmask, uint8 enable)
|
|
{
|
|
sint8 s8Ret;
|
|
uint32 val32;
|
|
s8Ret = nm_read_reg_with_ret(0x142c, &val32);
|
|
if(s8Ret != M2M_SUCCESS) {
|
|
M2M_ERR("[pullup_ctrl]: failed to read\n");
|
|
goto _EXIT;
|
|
}
|
|
if(enable) {
|
|
val32 &= ~pinmask;
|
|
} else {
|
|
val32 |= pinmask;
|
|
}
|
|
s8Ret = nm_write_reg(0x142c, val32);
|
|
if(s8Ret != M2M_SUCCESS) {
|
|
M2M_ERR("[pullup_ctrl]: failed to write\n");
|
|
goto _EXIT;
|
|
}
|
|
_EXIT:
|
|
return s8Ret;
|
|
}
|
|
#endif /* CONF_PERIPH */
|
|
|
|
sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid)
|
|
{
|
|
sint8 ret;
|
|
uint32 u32RegValue;
|
|
uint8 mac[6];
|
|
tstrGpRegs strgp = {0};
|
|
|
|
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
|
|
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
|
|
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
|
|
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
u32RegValue = strgp.u32Mac_efuse_mib;
|
|
|
|
if(!EFUSED_MAC(u32RegValue)) {
|
|
M2M_DBG("Default MAC\n");
|
|
m2m_memset(pu8MacAddr, 0, 6);
|
|
goto _EXIT_ERR;
|
|
}
|
|
|
|
M2M_DBG("OTP MAC\n");
|
|
u32RegValue >>=16;
|
|
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
|
|
m2m_memcpy(pu8MacAddr,mac,6);
|
|
if(pu8IsValid) *pu8IsValid = 1;
|
|
return ret;
|
|
|
|
_EXIT_ERR:
|
|
if(pu8IsValid) *pu8IsValid = 0;
|
|
return ret;
|
|
}
|
|
|
|
sint8 nmi_get_mac_address(uint8 *pu8MacAddr)
|
|
{
|
|
sint8 ret;
|
|
uint32 u32RegValue;
|
|
uint8 mac[6];
|
|
tstrGpRegs strgp = {0};
|
|
|
|
ret = nm_read_reg_with_ret(rNMI_GP_REG_0, &u32RegValue);
|
|
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
|
|
ret = nm_read_block(u32RegValue|0x30000,(uint8*)&strgp,sizeof(tstrGpRegs));
|
|
if(ret != M2M_SUCCESS) goto _EXIT_ERR;
|
|
u32RegValue = strgp.u32Mac_efuse_mib;
|
|
|
|
u32RegValue &=0x0000ffff;
|
|
ret = nm_read_block(u32RegValue|0x30000, mac, 6);
|
|
m2m_memcpy(pu8MacAddr, mac, 6);
|
|
|
|
return ret;
|
|
|
|
_EXIT_ERR:
|
|
return ret;
|
|
}
|