182 lines
4.3 KiB
C
182 lines
4.3 KiB
C
/**
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*
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* \file
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*
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* \brief This module contains SAMD21 BSP APIs implementation.
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*
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* Copyright (c) 2018 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#include "bsp/include/nm_bsp.h"
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#include "common/include/nm_common.h"
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#include "timer.h"
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#include "define.h"
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#include "BoardCfg.h"
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//#include <plib.h>
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//#include "atmel_start.h"
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//#include "winc_init.h"
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#ifndef CONF_WINC_EXT_INT_PIN
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#define CONF_WINC_EXT_INT_PIN 0
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#endif
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static tpfNmBspIsr gpfIsr = NULL;
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void __ISR(_EXTERNAL_0_VECTOR , ipl3) chip_isr(void)
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//static void chip_isr(void)
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{
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if (gpfIsr)
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{
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gpfIsr();
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}
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IFS0bits.INT0IF = 0;
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}
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/*
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* @fn nm_bsp_init
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* @brief Initialize BSP
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* @return 0 in case of success and -1 in case of failure
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*/
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sint8 nm_bsp_init(void)
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{
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gpfIsr = NULL;
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//
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//JFM Not necessary, we know our timer base is 1ms...
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// /* Make sure a 1ms Systick is configured. */
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// if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk && SysTick->CTRL & SysTick_CTRL_TICKINT_Msk)) {
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// delay_init(SysTick);
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// }
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return M2M_SUCCESS;
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}
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/**
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* @fn nm_bsp_deinit
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* @brief De-iInitialize BSP
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* @return 0 in case of success and -1 in case of failure
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*/
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sint8 nm_bsp_deinit(void)
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{
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return M2M_SUCCESS;
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}
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/**
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* @fn nm_bsp_reset
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* @brief Reset NMC1500 SoC by setting CHIP_EN and RESET_N signals low,
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* CHIP_EN high then RESET_N high
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*/
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void nm_bsp_reset(void)
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{
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// GP_DEBUG_1_PIN = 1;
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WIFI_CHP_EN_PIN = 0;
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WIFI_CHP_RST_PIN = 0;
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// Sleep(1); //JFM
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Sleep(100);
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WIFI_CHP_EN_PIN = 1;
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// Sleep(5); JFM
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Sleep(150);
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WIFI_CHP_RST_PIN = 1;
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// GP_DEBUG_1_PIN = 0;
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// gpio_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, false);
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// gpio_set_pin_level(CONF_WINC_PIN_RESET, false);
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// nm_bsp_sleep(1);
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// gpio_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, true);
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// nm_bsp_sleep(5);
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// gpio_set_pin_level(CONF_WINC_PIN_RESET, true);
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}
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/*
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* @fn nm_bsp_sleep
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* @brief Sleep in units of mSec
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* @param[IN] u32TimeMsec
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* Time in milliseconds
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*/
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void nm_bsp_sleep(uint32 u32TimeMsec)
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{
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Sleep(u32TimeMsec);
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// while (u32TimeMsec--) {
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// delay_ms(1);
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// }
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}
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/**
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* \internal Get the PIO hardware instance
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*
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* \param[in] pin The PIO pin
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*
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* \return The instance of PIO hardware
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*/
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/*
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* @fn nm_bsp_register_isr
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* @brief Register interrupt service routine
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* @param[IN] pfIsr
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* Pointer to ISR handler
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*/
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void nm_bsp_register_isr(tpfNmBspIsr pfIsr)
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{
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gpfIsr = pfIsr;
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//
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// ext_irq_register(CONF_WINC_EXT_INT_PIN, chip_isr);
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}
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/*
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* @fn nm_bsp_interrupt_ctrl
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* @brief Enable/Disable interrupts
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* @param[IN] u8Enable
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* '0' disable interrupts. '1' enable interrupts
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*/
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void nm_bsp_interrupt_ctrl(uint8 u8Enable)
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{
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if(u8Enable == 0)
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{
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IEC0bits.INT0IE = 0;
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}
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else
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{
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IEC0bits.INT0IE = 1;
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}
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// _ext_irq_enable(CONF_WINC_EXT_INT_PIN, u8Enable);
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}
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