219 lines
5.4 KiB
C
219 lines
5.4 KiB
C
/**
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*
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* \file
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*
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* \brief This module contains NMC1500 ASIC specific internal APIs.
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*
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* Copyright (c) 2015 - 2017 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _NMASIC_H_
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#define _NMASIC_H_
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#include "common/include/nm_common.h"
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#define NMI_PERIPH_REG_BASE 0x1000
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#define NMI_CHIPID (NMI_PERIPH_REG_BASE)
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#define rNMI_GP_REG_0 (0x149c)
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#define rNMI_GP_REG_1 (0x14A0)
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#define rNMI_GP_REG_2 (0xc0008)
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#define rNMI_GLB_RESET (0x1400)
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#define rNMI_BOOT_RESET_MUX (0x1118)
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#define NMI_STATE_REG (0x108c)
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#define BOOTROM_REG (0xc000c)
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#define NMI_REV_REG (0x207ac) /*Also, Used to load ATE firmware from SPI Flash and to ensure that it is running too*/
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#define NMI_REV_REG_ATE (0x1048) /*Revision info register in case of ATE FW*/
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#define M2M_WAIT_FOR_HOST_REG (0x207bc)
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#define M2M_FINISH_INIT_STATE 0x02532636UL
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#define M2M_FINISH_BOOT_ROM 0x10add09eUL
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#define M2M_START_FIRMWARE 0xef522f61UL
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#define M2M_START_PS_FIRMWARE 0x94992610UL
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#define M2M_ATE_FW_START_VALUE (0x3C1CD57D) /*Also, Change this value in boot_firmware if it will be changed here*/
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#define M2M_ATE_FW_IS_UP_VALUE \
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(0xD75DC1C3) /*Also, Change this value in ATE (Burst) firmware if it will be changed here*/
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#define REV_2B0 (0x2B0)
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#define REV_B0 (0x2B0)
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#define REV_3A0 (0x3A0)
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#define GET_CHIPID() nmi_get_chipid()
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#define ISNMC1000(id) ((((id)&0xfffff000) == 0x100000) ? 1 : 0)
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#define ISNMC1500(id) ((((id)&0xfffff000) == 0x150000) ? 1 : 0)
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#define ISNMC3000(id) ((((id)&0xfff00000) == 0x300000) ? 1 : 0)
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#define REV(id) (((id)&0x00000fff))
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#define EFUSED_MAC(value) (value & 0xffff0000)
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#define rHAVE_SDIO_IRQ_GPIO_BIT (NBIT0)
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#define rHAVE_USE_PMU_BIT (NBIT1)
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#define rHAVE_SLEEP_CLK_SRC_RTC_BIT (NBIT2)
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#define rHAVE_SLEEP_CLK_SRC_XO_BIT (NBIT3)
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#define rHAVE_EXT_PA_INV_TX_RX (NBIT4)
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#define rHAVE_LEGACY_RF_SETTINGS (NBIT5)
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#define rHAVE_LOGS_DISABLED_BIT (NBIT6)
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#define rHAVE_ETHERNET_MODE_BIT (NBIT7)
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#define rHAVE_RESERVED1_BIT (NBIT8)
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#define rHAVE_RESERVED2_BIT (NBIT9)
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#define rHAVE_XO_XTALGM2_DIS_BIT (NBIT10)
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typedef struct {
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uint32 u32Mac_efuse_mib;
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uint32 u32Firmware_Ota_rev;
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} tstrGpRegs;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* @fn cpu_halt
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* @brief
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*/
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sint8 cpu_halt(void);
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/*
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* @fn chip_sleep
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* @brief
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*/
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sint8 chip_sleep(void);
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/*
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* @fn chip_wake
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* @brief
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*/
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sint8 chip_wake(void);
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/*
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* @fn chip_idle
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* @brief
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*/
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void chip_idle(void);
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/*
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* @fn enable_interrupts
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* @brief
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*/
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sint8 enable_interrupts(void);
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/*
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* @fn cpu_start
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* @brief
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*/
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sint8 cpu_start(void);
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/*
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* @fn nmi_get_chipid
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* @brief
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*/
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uint32 nmi_get_chipid(void);
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/*
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* @fn nmi_get_rfrevid
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* @brief
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*/
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uint32 nmi_get_rfrevid(void);
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/*
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* @fn restore_pmu_settings_after_global_reset
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* @brief
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*/
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void restore_pmu_settings_after_global_reset(void);
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/*
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* @fn nmi_update_pll
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* @brief
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*/
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void nmi_update_pll(void);
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/*
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* @fn nmi_set_sys_clk_src_to_xo
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* @brief
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*/
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void nmi_set_sys_clk_src_to_xo(void);
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/*
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* @fn chip_reset
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* @brief
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*/
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sint8 chip_reset(void);
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/*
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* @fn wait_for_bootrom
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* @brief
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*/
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sint8 wait_for_bootrom(uint8);
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/*
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* @fn wait_for_firmware_start
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* @brief
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*/
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sint8 wait_for_firmware_start(uint8);
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/*
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* @fn chip_deinit
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* @brief
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*/
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sint8 chip_deinit(void);
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/*
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* @fn chip_reset_and_cpu_halt
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* @brief
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*/
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sint8 chip_reset_and_cpu_halt(void);
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/*
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* @fn set_gpio_dir
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* @brief
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*/
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sint8 set_gpio_dir(uint8 gpio, uint8 dir);
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/*
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* @fn set_gpio_val
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* @brief
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*/
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sint8 set_gpio_val(uint8 gpio, uint8 val);
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/*
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* @fn get_gpio_val
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* @brief
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*/
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sint8 get_gpio_val(uint8 gpio, uint8 *val);
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/*
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* @fn pullup_ctrl
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* @brief
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*/
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sint8 pullup_ctrl(uint32 pinmask, uint8 enable);
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/*
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* @fn nmi_get_otp_mac_address
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* @brief
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*/
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sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 *pu8IsValid);
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/*
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* @fn nmi_get_mac_address
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* @brief
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*/
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sint8 nmi_get_mac_address(uint8 *pu8MacAddr);
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/*
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* @fn chip_apply_conf
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* @brief
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*/
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sint8 chip_apply_conf(uint32 u32conf);
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#ifdef __cplusplus
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}
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#endif
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#endif /*_NMASIC_H_*/
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